Design of a Low Power Low Voltage Full Adder
نویسندگان
چکیده
In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder. This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology is used with supply voltage=1V and 10MHz frequency. Dual threshold model file (version 49) is used to observe the o1utput.
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